2020/04/01

【技術報告】IEEE Transactions on Computers/R.Ueno, S.Morioka, N.Miura, K.Matsuda, M.Nagata, S.Bhasin, Y.Mathieu, T.Graba, J.L.Danger, N.Homma, “High Throughput/Gate AES Hardware Architectures Based on Datapath Compuression”, IEEE Trans. on Computers, Vol.69, Issue 4, pp.534-548, 2020.

【学会名】
IEEE Transactions on Computers

【タイトル】

R.Ueno, S.Morioka, N.Miura, K.Matsuda, M.Nagata, S.Bhasin, Y.Mathieu, T.Graba, J.L.Danger, N.Homma, “High Throughput/Gate AES Hardware Architectures Based on Datapath Compuression”, IEEE Trans. on Computers, Vol.69, Issue 4, pp.534-548, 2020.

【リンク】

https://ieeexplore.ieee.org/document/8922779